1. Field of the Invention
The present invention relates generally to power amplifiers having power transistors, and more specifically to a structure for monitoring the power output of individual power transistors of a solid state power amplifier.
2. Description of the Prior Art
Solid state power amplifiers often contain a number of power transistors and the power output of a power amplifier is dependent to some extent on the integrity of individual power transistors in the power amplifier. In a power amplifier having N transistors, it can be difficult to tune individual power transistors to achieve best performance, because the power output of each power transistor, which contributes to the power output of the power amplifier, may not be easily measured.
The effect on the power output of the power amplifier will vary with the number and value of power transistors used. The fewer power transistors a power amplifier has, the more effect one failing transistor will have on the overall power output of the power amplifier. For instance, a power amplifier having only four power transistors may experience a significant power loss if one of the four power transistors fails. On the other hand, a power amplifier having a large number of power transistors may experience little or no effect on the power output of the power amplifier if a single power transistor fails.
Additionally, the envelope of an RF/microwave carrier signal presented to the power amplifier may be degradated at the output of the entire power amplifier if each power transistor does not achieve optimum rise and fall times. This consideration is especially valid for an RF/microwave carrier subjected to rapid amplitude changes, as is often the case in pulse modulated RF/microwave carriers. Thus, there is a current need in the art to be able to quickly tune the matching circuits of the power transistors of a power amplifier in order to obtain the optimum rise and fall times from each power transistor.
In addition to difficulty in measuring the power output of power transistors in a power amplifier, possible reflection problems exist when the impedance of a power transistor is inadequately tuned to the impedance of its source and its load. The benefits of a correct match include minimizing power reflected back into the power transistor source and minimizing power dissipation or loss between the power transistor and its load, as well as maintaining a low power transistor junction temperature. For these reasons, it is desirable to be able to tune the impedance of the input matching circuit and output matching circuit of a power transistor upon being placed into a power amplifier and then, again, during operation as necessary, such that a good conjugate match is established and maintained throughout operation.
Tuning the input and output matching circuits of a power transistor enables a good impedance match between the power transistor and its load to be achieved and maintained so that power transfer is maximized. Additionally, quickly tuning the amplitude of the power transistors will help ensure the best possible rise and fall time for each power transistor; thus, the output signal of the entire power amplifier will be correspondingly improved.
Power amplifier circuitry which makes it possible to measure critical parameters of power transistors does exist in the prior art. However, these solutions tend to be discrete and thus costly. Presently there is not a convenient way to directly determine parameters such as rise and fall times and impedance matching in a time and cost efficient manner. Thus, there is a current need in the art to be able to monitor and modify the output signals of power transistors in a direct way.